The 264 Quad Sample & Hold consists of four independent sample & hold circuits which can be configured to either sample on the rising edge of the pulse or track for the duration of the pulse. Each of the outputs can be modified by the Offset control and FM modulation.
The polyphonic support consists of two independent functions - a separate/common CV switch and 2 to 4 stage pulse generator. The switch simply disconnects the four CV input jacks and connects all four sample & hold circuits to the common CV input. The 2 to 4 stage pulse generator generates sequenced pulse outputs from a common pulse input. The Pulse Output jacks need to be connected to the Pulse Input jacks for the number of voices selected. With the switch in the Common position, the CV sampling is then sequenced through the number of stages selected.
For example, on the first pulse, the CV is sampled and held in the first channel. On the second pulse the CV is sampled and held in the second channel. When the maximum number of voices is reached, the sampling reverts back to the first channel. Thus a CV can be sampled and routed along with its associated pulse input to four VCOs and sustained over the number of voice pulse inputs. This differs from an analog shift register where the CV to a particular VCO is maintained only for the duration between common pulses.
When set to 2 or 3 voices the additional shift registers may be operated with their own pulse input but their CV input is common as controlled by the switch. Note also that the Common switch need not be used with the pulse generator. This allows sequencing of the sample & holds with separate CV inputs.
The panel wiring is complete prior to adding the PCBs. The in-line terminal strips are difficult to find so I fabricated both from 6 lug strips. The 9 lug is two strips pieced together and the 5 lug is shortened one terminal. I also used a terminal strip between two banana jacks for the ground connection to the resistors as it was better than trying to use the far left terminal strip. The left terminal strip is for routing power to the two PCBs.
I eliminated the +24V supply so the red wire connects +24V for IC4 to +15V and the zener is replaced with a 0R resistor to supply -15V. See modifications below for details.
PCB2 uses the MC846 DTL quad NAND gates which have internal resistor pull-ups. These are a somewhat rare and the leads are typically corroded so I use 74LS03 open collector with 1/8W 2K4 resistor pull-ups. All transistors are 2N3904 and 2N3906.
I wired the PCBs so they folded to opposite sides to be accessible for service. Construction of this module was quite tedious.
The boards fold together and make a very compact and dense module. The shorter standoffs are 12 mm to allow clearance for the LED terminal strip.
This image shows a single channel sample and hold with no offset.
This image shows a single channel track and hold with no offset.
This image shows a two stage polyphonic sample and hold with no offset.
This image shows a two stage polyphonic track and hold with no offset.
This image shows a two stage polyphonic track and hold with negative offset.
This image shows a higher input frequency two stage polyphonic track and hold with no offset.
This image shows a four stage polyphonic track and hold with no offset. Only the first two channels are shown on a four channel scope. You can see the two pulse gap in the magenta and green traces where stages 3 and 4 are.
The module will not function as an analog shift register by simply patching a CV Output to the next CV Input. Like all sample and hold cells, they are really track and hold cells. "Sampling" occurs when the control pulse is sufficiently narrow to make the tracking time insignificant.
Analog shift registers work instead by using analog switches to route inputs and outputs to and from each cell. On each pulse the CV input is switched to the last cell in the sequence and the outputs are switched to provide the correct sequence. Only one cell is ever sampled at a time. A pulse counter controls the switch sequencing.
For example, on the first clock pulse the CV input is switched say to cell 1. Cell 1 is switched to output 1, cell 2 is switched to output 2, etc. providing the correct sequence. On the next clock pulse the CV input is switched to reuse the last cell which in this case would be cell 4, and cell 4 is switched to output 1. Cell 1 is switched to output 2, cell 2 is switched to output 3, etc. providing the correct sequence.
The control pulse on the 264 is 424 ÁS which provides adequate time for the sampling capacitor to reach the desired voltage.
Once sampled, the output voltage remains stable. However if resampling a constant voltage the CV Output will vary slightly. Using a precision reference supply with a 1 Hz Pulse I measured a 17 mV range deviation in the CV Output voltage. At 1.2V/Oct this represents a 17 cent error.
I found that the output of the LM301 had both high frequency oscillations and erratic behavior. To compensate for losses in the JFET follower, Don took the feedback for the LM301 after the JFET follower output. However, this output is the sampled voltage. When the Pulse Input goes false the LM301 output jumps around. Sample & hold circuits have improved a lot in the 50+ years since this module was designed. A low bias op-amp could be used eliminating the need for the JFET follower and the LM301 feedback could be taken from its output. I didn't pursue this further since the PCB was not designed for high impedance low current signals.
The high frequency oscillations were the more significant issue. I found that eliminating the 470K resistor and simply connecting the 22 pF compensation capacitor between pins 1 and 8 eliminated the high frequency oscillations. The LM301 specifies 30 pF but I simply used the existing 22 pF capacitors.
Using a LT1672 rail-to-rail op-amp for IC4 and powering it from +/-15V yielded a -4.8V to +13.8V CV range which is quite adequate for both audio signals and CV voltages.
The CV input is attenuated by 20% and the output has gain of 1.25X. The resistors are 1% resulting in a gain error of up to +/-4% in each cell. There are no trimmers for op-amp offset so the CV Outputs can also have a small +/- voltage. Using a 5.018V precision reference on all inputs and sampling with a 1 Hz Pulse I measured CV Output voltages of 5.004, 4.997, 5.003, and 5.003V. These are all within 0.5%.
The one oddity that remains is somewhat random output when sampling with no CV Input. The output jumps around a bit although the levels are quite small. I believe this is due to the LM301 feedback after the sample capacitor.
Connecting the CV input to a source with less than 4K7 impedance eliminates these random variations. Here the input is simply grounded.
The other oddity is the Offset control. For some odd reason Don biased the + input of IC1 to 2.5V. This results in significant added voltage to the CV Outputs when the control is centered. This makes no sense to me. I chose to rewire the circuit so the Offset control runs on +/-15V so at center is 0V. I added anti-parallel diodes to create a 0.6V dead zone at the center and eliminated the 2.5V offset. I decreased the gain by 50% to compensate for doubling the voltage. I also changed IC1 to a TL071 to decrease any offset voltage. The dead zone is better but is still small. I might recommend a second set of diodes in series to double the dead zone to 1.2V.
264 PCB1 modifications