Buchla 277 Signal Delay Unit

A customer sent me a partially built 277 Signal Delay Unit and I finished assembly.

 

I did bus the grounds between output pairs rather than running two separate grounds to each jack.  The eeproms are not installed in this photo.

 

I assembled it according to the BOM and build thread with one exception.  I chose to use the LED bezel and clip rather than using epoxy to attach the bezel to the panel.  I find that attaching components to front panels with epoxy isn't the most reliable and can be a bit messy.  I chose instead to mount the LED in the bezel with the clip and wire it to the PCB so the panel could later be removed for repairs if necessary.  

 

 

Operation

This image shows the power-on delay of 128 mS to start transferring the contents of the eeprom.

 

This image shows the input and the 1/2T, 3/4T, and 1T outputs.

 

This image shows the maximum delay of 2 seconds.

 

The minimum delay is a bit more complicated.  There is processing time from the input to the output and then delay time between the outputs.  The input rising edge is at the first cursor and all four outputs are shown.  The delay from the input to the 1/4 output is 2.3 ms.

 

The delay from the 1/4T output to the 1/2T and from the 3/4T to 1T output is 929 uS.  There is extra processing time of 1.4 mS from the input to the 1/4T output.  This same delay can be seen from the 1/2T to 3/4T output when the second Spin FV-1 has to process the 1/2T input.

 

Thus the minimum delay is 6.5 mS but the delays between the four outputs are asymmetrical at 0.9mS, 2.3mS, 0.9mS.

 

 

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